1. Field of the Invention
Present invention relates to a semiconductor memory device and, more particularly, to a configuration of sense amplifier and an IO line wiring pattern of the semiconductor memory device.
2. Description of Related Art
FIG. 10 is an enlarged view of a part of an array portion among conventional semiconductor memory device.
In FIG. 10, LIO is first IO line connected to the sense amplifier which amplifies a data of a memory cell, and is arranged in a SAMP row region formed the sense amplifier. On the other hand, GIO is second IO line for connecting with LIO and supplying data to the data amplifier (DAMP). Here, GIO is formed on a sub WORD driver (SWD) formation region and on a crossing portion.
The memory cells are arranged with 8xc3x978 sets. Between each memory cell, the SAMP row are arranged in a lateral direction in paper of FIG. 10, and the SWD row are arranged in a vertical direction in paper of FIG. 10. The crossing portions are arranged between each SAMP row and the SWD row respectively.
FIG. 8 is an enlarged view of a portion L of FIG. 10, and FIG. 9 is a simplified cross-sectional view which cut a drawing of FIG. 8 with a broken line X.
In FIG. 8, input/output wiring group T and eight lines of GIO are wired on the SWD, and it""s cross-sectional view is shown in FIG. 9.
FIG. 11 is an enlarged view of the crossing portion circumference where LIO and GIO intersect, and FIG. 12 is an enlarged view of a switch element arrangement portion circumference A which connects LIO and GIO. As shown in FIG. 11, LIO and GIO are connected through SW1. The SW1 serves as a transfer gate, as shown in FIG. 12.
In FIG. 11, there are eight lines of GIO to four lines of LIO. It is because, in the vertical direction of the paper of the FIG. 10, addresses differ in odd steps and even steps of a sense amplifier row.
In the conventional array portion, eight lines of GIO are wired on SWD and on the crossing portion. For this reason, the wiring groups T and GIO on the SWD occupy an area larger than the SWD. Therefore, it is not easy to downsize the SWD.
The semiconductor memory device of present invention has a memory cell, a sense amplifier for amplifying a data of the memory cell, first IO line connected to the sense amplifier, and second IO line which connected through a switch to first IO line, wherein the second IO line is arranged on the memory cell.
The above-mentioned switch is formed in the region in which the sense amplifier is formed.
Second IO line is connected to data amplifier.
Furthermore, the semiconductor memory device of present invention has the sense amplifier for amplifying the data of a memory cell. And the semiconductor memory device also has an IO line for supplying the data from the sense amplifier to data amplifier. As for the semiconductor memory device, the IO line is arranged on the memory cell.
The IO line consists of the first and second wiring portions, and it has the switch element which connects the first and second wiring portions.
The switch element is in the sense amplifier formation region.